//! This file is auto-generated by tools/update_cpu_features.zig.

const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;

pub const Feature = enum {
    @"32bit",
    @"64bit",
    a,
    add_load_fusion,
    addi_load_fusion,
    andes45,
    auipc_addi_fusion,
    auipc_load_fusion,
    b,
    bfext_fusion,
    c,
    conditional_cmv_fusion,
    d,
    disable_latency_sched_heuristic,
    disable_misched_load_clustering,
    disable_misched_store_clustering,
    disable_postmisched_load_clustering,
    disable_postmisched_store_clustering,
    dlen_factor_2,
    e,
    enable_vsetvli_sched_heuristic,
    exact_asm,
    experimental,
    experimental_p,
    experimental_rvm23u32,
    experimental_smpmpmt,
    experimental_svukte,
    experimental_xrivosvisni,
    experimental_xrivosvizip,
    experimental_xsfmclic,
    experimental_xsfsclic,
    experimental_zibi,
    experimental_zicfilp,
    experimental_zicfiss,
    experimental_zvbc32e,
    experimental_zvfbfa,
    experimental_zvfofp8min,
    experimental_zvkgs,
    experimental_zvqdotq,
    f,
    forced_atomics,
    h,
    i,
    ld_add_fusion,
    log_vrgather,
    lui_addi_fusion,
    lui_load_fusion,
    m,
    mips_p8700,
    no_default_unroll,
    no_sink_splat_operands,
    no_trailing_seq_cst_fence,
    optimized_nf2_segment_load_store,
    optimized_nf3_segment_load_store,
    optimized_nf4_segment_load_store,
    optimized_nf5_segment_load_store,
    optimized_nf6_segment_load_store,
    optimized_nf7_segment_load_store,
    optimized_nf8_segment_load_store,
    optimized_zero_stride_load,
    permissive_zalrsc,
    predictable_select_expensive,
    prefer_vsetvli_over_read_vlenb,
    prefer_w_inst,
    q,
    relax,
    reserve_x1,
    reserve_x10,
    reserve_x11,
    reserve_x12,
    reserve_x13,
    reserve_x14,
    reserve_x15,
    reserve_x16,
    reserve_x17,
    reserve_x18,
    reserve_x19,
    reserve_x2,
    reserve_x20,
    reserve_x21,
    reserve_x22,
    reserve_x23,
    reserve_x24,
    reserve_x25,
    reserve_x26,
    reserve_x27,
    reserve_x28,
    reserve_x29,
    reserve_x3,
    reserve_x30,
    reserve_x31,
    reserve_x4,
    reserve_x5,
    reserve_x6,
    reserve_x7,
    reserve_x8,
    reserve_x9,
    rva20s64,
    rva20u64,
    rva22s64,
    rva22u64,
    rva23s64,
    rva23u64,
    rvb23s64,
    rvb23u64,
    rvi20u32,
    rvi20u64,
    save_restore,
    sdext,
    sdtrig,
    sha,
    shcounterenw,
    shgatpa,
    shifted_zextw_fusion,
    shlcofideleg,
    short_forward_branch_ialu,
    short_forward_branch_iload,
    short_forward_branch_iminmax,
    short_forward_branch_imul,
    shtvala,
    shvsatpa,
    shvstvala,
    shvstvecd,
    shxadd_load_fusion,
    single_element_vec_fp64,
    smaia,
    smcdeleg,
    smcntrpmf,
    smcsrind,
    smctr,
    smdbltrp,
    smepmp,
    smmpm,
    smnpm,
    smrnmi,
    smstateen,
    ssaia,
    ssccfg,
    ssccptr,
    sscofpmf,
    sscounterenw,
    sscsrind,
    ssctr,
    ssdbltrp,
    ssnpm,
    sspm,
    ssqosid,
    ssstateen,
    ssstrict,
    sstc,
    sstvala,
    sstvecd,
    ssu64xl,
    supm,
    svade,
    svadu,
    svbare,
    svinval,
    svnapot,
    svpbmt,
    svvptc,
    tagged_globals,
    unaligned_scalar_mem,
    unaligned_vector_mem,
    use_postra_scheduler,
    v,
    ventana_veyron,
    vl_dependent_latency,
    vxrm_pipeline_flush,
    xandesbfhcvt,
    xandesperf,
    xandesvbfhcvt,
    xandesvdot,
    xandesvpackfph,
    xandesvsinth,
    xandesvsintload,
    xcvalu,
    xcvbi,
    xcvbitmanip,
    xcvelw,
    xcvmac,
    xcvmem,
    xcvsimd,
    xmipscbop,
    xmipscmov,
    xmipsexectl,
    xmipslsp,
    xqccmp,
    xqci,
    xqcia,
    xqciac,
    xqcibi,
    xqcibm,
    xqcicli,
    xqcicm,
    xqcics,
    xqcicsr,
    xqciint,
    xqciio,
    xqcilb,
    xqcili,
    xqcilia,
    xqcilo,
    xqcilsm,
    xqcisim,
    xqcisls,
    xqcisync,
    xsfcease,
    xsfmm128t,
    xsfmm16t,
    xsfmm32a16f,
    xsfmm32a32f,
    xsfmm32a8f,
    xsfmm32a8i,
    xsfmm32t,
    xsfmm64a64f,
    xsfmm64t,
    xsfmmbase,
    xsfvcp,
    xsfvfbfexp16e,
    xsfvfexp16e,
    xsfvfexp32e,
    xsfvfexpa,
    xsfvfexpa64e,
    xsfvfnrclipxfqf,
    xsfvfwmaccqqq,
    xsfvqmaccdod,
    xsfvqmaccqoq,
    xsifivecdiscarddlone,
    xsifivecflushdlone,
    xsmtvdot,
    xtheadba,
    xtheadbb,
    xtheadbs,
    xtheadcmo,
    xtheadcondmov,
    xtheadfmemidx,
    xtheadmac,
    xtheadmemidx,
    xtheadmempair,
    xtheadsync,
    xtheadvdot,
    xventanacondops,
    xwchc,
    za128rs,
    za64rs,
    zaamo,
    zabha,
    zacas,
    zalasr,
    zalrsc,
    zama16b,
    zawrs,
    zba,
    zbb,
    zbc,
    zbkb,
    zbkc,
    zbkx,
    zbs,
    zca,
    zcb,
    zcd,
    zce,
    zcf,
    zclsd,
    zcmop,
    zcmp,
    zcmt,
    zdinx,
    zexth_fusion,
    zextw_fusion,
    zfa,
    zfbfmin,
    zfh,
    zfhmin,
    zfinx,
    zhinx,
    zhinxmin,
    zic64b,
    zicbom,
    zicbop,
    zicboz,
    ziccamoa,
    ziccamoc,
    ziccif,
    zicclsm,
    ziccrse,
    zicntr,
    zicond,
    zicsr,
    zifencei,
    zihintntl,
    zihintpause,
    zihpm,
    zilsd,
    zilsd_4byte_align,
    zimop,
    zk,
    zkn,
    zknd,
    zkne,
    zknh,
    zkr,
    zks,
    zksed,
    zksh,
    zkt,
    zmmul,
    ztso,
    zvbb,
    zvbc,
    zve32f,
    zve32x,
    zve64d,
    zve64f,
    zve64x,
    zvfbfmin,
    zvfbfwma,
    zvfh,
    zvfhmin,
    zvkb,
    zvkg,
    zvkn,
    zvknc,
    zvkned,
    zvkng,
    zvknha,
    zvknhb,
    zvks,
    zvksc,
    zvksed,
    zvksg,
    zvksh,
    zvkt,
    zvl1024b,
    zvl128b,
    zvl16384b,
    zvl2048b,
    zvl256b,
    zvl32768b,
    zvl32b,
    zvl4096b,
    zvl512b,
    zvl64b,
    zvl65536b,
    zvl8192b,
};

pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;

pub const all_features = blk: {
    @setEvalBranchQuota(2000);
    const len = @typeInfo(Feature).@"enum".field_names.len;
    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
    var result: [len]CpuFeature = undefined;
    result[@backingInt(Feature.@"32bit")] = .{
        .llvm_name = "32bit",
        .description = "Implements RV32",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.@"64bit")] = .{
        .llvm_name = "64bit",
        .description = "Implements RV64",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.a)] = .{
        .llvm_name = "a",
        .description = "'A' (Atomic Instructions)",
        .dependencies = featureSet(&[_]Feature{
            .zaamo,
            .zalrsc,
        }),
    };
    result[@backingInt(Feature.add_load_fusion)] = .{
        .llvm_name = "add-load-fusion",
        .description = "Enable ADD(.UW) + load macrofusion",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.addi_load_fusion)] = .{
        .llvm_name = "addi-load-fusion",
        .description = "Enable ADDI + load macrofusion",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.andes45)] = .{
        .llvm_name = "andes45",
        .description = "Andes 45-Series processors",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.auipc_addi_fusion)] = .{
        .llvm_name = "auipc-addi-fusion",
        .description = "Enable AUIPC+ADDI macrofusion",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.auipc_load_fusion)] = .{
        .llvm_name = "auipc-load-fusion",
        .description = "Enable AUIPC + load macrofusion",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.b)] = .{
        .llvm_name = "b",
        .description = "'B' (the collection of the Zba, Zbb, Zbs extensions)",
        .dependencies = featureSet(&[_]Feature{
            .zba,
            .zbb,
            .zbs,
        }),
    };
    result[@backingInt(Feature.bfext_fusion)] = .{
        .llvm_name = "bfext-fusion",
        .description = "Enable SLLI+SRLI (bitfield extract) macrofusion",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.c)] = .{
        .llvm_name = "c",
        .description = "'C' (Compressed Instructions)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.conditional_cmv_fusion)] = .{
        .llvm_name = "conditional-cmv-fusion",
        .description = "Enable branch+c.mv fusion",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.d)] = .{
        .llvm_name = "d",
        .description = "'D' (Double-Precision Floating-Point)",
        .dependencies = featureSet(&[_]Feature{
            .f,
        }),
    };
    result[@backingInt(Feature.disable_latency_sched_heuristic)] = .{
        .llvm_name = "disable-latency-sched-heuristic",
        .description = "Disable latency scheduling heuristic",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.disable_misched_load_clustering)] = .{
        .llvm_name = "disable-misched-load-clustering",
        .description = "Disable load clustering in the machine scheduler",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.disable_misched_store_clustering)] = .{
        .llvm_name = "disable-misched-store-clustering",
        .description = "Disable store clustering in the machine scheduler",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.disable_postmisched_load_clustering)] = .{
        .llvm_name = "disable-postmisched-load-clustering",
        .description = "Disable PostRA load clustering in the machine scheduler",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.disable_postmisched_store_clustering)] = .{
        .llvm_name = "disable-postmisched-store-clustering",
        .description = "Disable PostRA store clustering in the machine scheduler",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.dlen_factor_2)] = .{
        .llvm_name = "dlen-factor-2",
        .description = "Vector unit DLEN(data path width) is half of VLEN",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.e)] = .{
        .llvm_name = "e",
        .description = "'E' (Embedded Instruction Set with 16 GPRs)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.enable_vsetvli_sched_heuristic)] = .{
        .llvm_name = "enable-vsetvli-sched-heuristic",
        .description = "Enable vsetvli-based scheduling heuristic",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.exact_asm)] = .{
        .llvm_name = "exact-asm",
        .description = "Enable Exact Assembly (Disables Compression and Relaxation)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.experimental)] = .{
        .llvm_name = "experimental",
        .description = "Experimental intrinsics",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.experimental_p)] = .{
        .llvm_name = "experimental-p",
        .description = "'P' ('Base P' (Packed SIMD))",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.experimental_rvm23u32)] = .{
        .llvm_name = "experimental-rvm23u32",
        .description = "RISC-V experimental-rvm23u32 profile",
        .dependencies = featureSet(&[_]Feature{
            .@"32bit",
            .b,
            .i,
            .m,
            .zce,
            .zcmop,
            .zicbop,
            .zicond,
            .zihintntl,
            .zihintpause,
            .zimop,
        }),
    };
    result[@backingInt(Feature.experimental_smpmpmt)] = .{
        .llvm_name = "experimental-smpmpmt",
        .description = "'Smpmpmt' (PMP-based Memory Types Extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.experimental_svukte)] = .{
        .llvm_name = "experimental-svukte",
        .description = "'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.experimental_xrivosvisni)] = .{
        .llvm_name = "experimental-xrivosvisni",
        .description = "'XRivosVisni' (Rivos Vector Integer Small New)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.experimental_xrivosvizip)] = .{
        .llvm_name = "experimental-xrivosvizip",
        .description = "'XRivosVizip' (Rivos Vector Register Zips)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.experimental_xsfmclic)] = .{
        .llvm_name = "experimental-xsfmclic",
        .description = "'XSfmclic' (SiFive CLIC Machine-mode CSRs)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.experimental_xsfsclic)] = .{
        .llvm_name = "experimental-xsfsclic",
        .description = "'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.experimental_zibi)] = .{
        .llvm_name = "experimental-zibi",
        .description = "'Zibi' (Branch with Immediate)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.experimental_zicfilp)] = .{
        .llvm_name = "experimental-zicfilp",
        .description = "'Zicfilp' (Landing pad)",
        .dependencies = featureSet(&[_]Feature{
            .zicsr,
        }),
    };
    result[@backingInt(Feature.experimental_zicfiss)] = .{
        .llvm_name = "experimental-zicfiss",
        .description = "'Zicfiss' (Shadow stack)",
        .dependencies = featureSet(&[_]Feature{
            .zicsr,
            .zimop,
        }),
    };
    result[@backingInt(Feature.experimental_zvbc32e)] = .{
        .llvm_name = "experimental-zvbc32e",
        .description = "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.experimental_zvfbfa)] = .{
        .llvm_name = "experimental-zvfbfa",
        .description = "'Zvfbfa' (Additional BF16 vector compute support)",
        .dependencies = featureSet(&[_]Feature{
            .zfbfmin,
            .zve32f,
        }),
    };
    result[@backingInt(Feature.experimental_zvfofp8min)] = .{
        .llvm_name = "experimental-zvfofp8min",
        .description = "'Zvfofp8min' (Vector OFP8 Converts)",
        .dependencies = featureSet(&[_]Feature{
            .zve32f,
        }),
    };
    result[@backingInt(Feature.experimental_zvkgs)] = .{
        .llvm_name = "experimental-zvkgs",
        .description = "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)",
        .dependencies = featureSet(&[_]Feature{
            .zvkg,
        }),
    };
    result[@backingInt(Feature.experimental_zvqdotq)] = .{
        .llvm_name = "experimental-zvqdotq",
        .description = "'Zvqdotq' (Vector quad widening 4D Dot Product)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.f)] = .{
        .llvm_name = "f",
        .description = "'F' (Single-Precision Floating-Point)",
        .dependencies = featureSet(&[_]Feature{
            .zicsr,
        }),
    };
    result[@backingInt(Feature.forced_atomics)] = .{
        .llvm_name = "forced-atomics",
        .description = "Assume that lock-free native-width atomics are available",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.h)] = .{
        .llvm_name = "h",
        .description = "'H' (Hypervisor)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.i)] = .{
        .llvm_name = "i",
        .description = "'I' (Base Integer Instruction Set)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ld_add_fusion)] = .{
        .llvm_name = "ld-add-fusion",
        .description = "Enable LD+ADD macrofusion",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.log_vrgather)] = .{
        .llvm_name = "log-vrgather",
        .description = "Has vrgather.vv with LMUL*log2(LMUL) latency",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.lui_addi_fusion)] = .{
        .llvm_name = "lui-addi-fusion",
        .description = "Enable LUI+ADDI macro fusion",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.lui_load_fusion)] = .{
        .llvm_name = "lui-load-fusion",
        .description = "Enable LUI + load macrofusion",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.m)] = .{
        .llvm_name = "m",
        .description = "'M' (Integer Multiplication and Division)",
        .dependencies = featureSet(&[_]Feature{
            .zmmul,
        }),
    };
    result[@backingInt(Feature.mips_p8700)] = .{
        .llvm_name = "mips-p8700",
        .description = "MIPS p8700 processor",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.no_default_unroll)] = .{
        .llvm_name = "no-default-unroll",
        .description = "Disable default unroll preference.",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.no_sink_splat_operands)] = .{
        .llvm_name = "no-sink-splat-operands",
        .description = "Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.no_trailing_seq_cst_fence)] = .{
        .llvm_name = "no-trailing-seq-cst-fence",
        .description = "Disable trailing fence for seq-cst store.",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.optimized_nf2_segment_load_store)] = .{
        .llvm_name = "optimized-nf2-segment-load-store",
        .description = "vlseg2eN.v and vsseg2eN.v are implemented as a wide memory op and shuffle",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.optimized_nf3_segment_load_store)] = .{
        .llvm_name = "optimized-nf3-segment-load-store",
        .description = "vlseg3eN.v and vsseg3eN.v are implemented as a wide memory op and shuffle",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.optimized_nf4_segment_load_store)] = .{
        .llvm_name = "optimized-nf4-segment-load-store",
        .description = "vlseg4eN.v and vsseg4eN.v are implemented as a wide memory op and shuffle",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.optimized_nf5_segment_load_store)] = .{
        .llvm_name = "optimized-nf5-segment-load-store",
        .description = "vlseg5eN.v and vsseg5eN.v are implemented as a wide memory op and shuffle",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.optimized_nf6_segment_load_store)] = .{
        .llvm_name = "optimized-nf6-segment-load-store",
        .description = "vlseg6eN.v and vsseg6eN.v are implemented as a wide memory op and shuffle",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.optimized_nf7_segment_load_store)] = .{
        .llvm_name = "optimized-nf7-segment-load-store",
        .description = "vlseg7eN.v and vsseg7eN.v are implemented as a wide memory op and shuffle",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.optimized_nf8_segment_load_store)] = .{
        .llvm_name = "optimized-nf8-segment-load-store",
        .description = "vlseg8eN.v and vsseg8eN.v are implemented as a wide memory op and shuffle",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.optimized_zero_stride_load)] = .{
        .llvm_name = "optimized-zero-stride-load",
        .description = "Optimized (perform fewer memory operations)zero-stride vector load",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.permissive_zalrsc)] = .{
        .llvm_name = "permissive-zalrsc",
        .description = "Implementation permits non-base instructions between LR/SC pairs",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.predictable_select_expensive)] = .{
        .llvm_name = "predictable-select-expensive",
        .description = "Prefer likely predicted branches over selects",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.prefer_vsetvli_over_read_vlenb)] = .{
        .llvm_name = "prefer-vsetvli-over-read-vlenb",
        .description = "Prefer vsetvli over read vlenb CSR to calculate VLEN",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.prefer_w_inst)] = .{
        .llvm_name = "prefer-w-inst",
        .description = "Prefer instructions with W suffix",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.q)] = .{
        .llvm_name = "q",
        .description = "'Q' (Quad-Precision Floating-Point)",
        .dependencies = featureSet(&[_]Feature{
            .d,
        }),
    };
    result[@backingInt(Feature.relax)] = .{
        .llvm_name = "relax",
        .description = "Enable Linker relaxation.",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x1)] = .{
        .llvm_name = "reserve-x1",
        .description = "Reserve X1",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x10)] = .{
        .llvm_name = "reserve-x10",
        .description = "Reserve X10",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x11)] = .{
        .llvm_name = "reserve-x11",
        .description = "Reserve X11",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x12)] = .{
        .llvm_name = "reserve-x12",
        .description = "Reserve X12",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x13)] = .{
        .llvm_name = "reserve-x13",
        .description = "Reserve X13",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x14)] = .{
        .llvm_name = "reserve-x14",
        .description = "Reserve X14",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x15)] = .{
        .llvm_name = "reserve-x15",
        .description = "Reserve X15",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x16)] = .{
        .llvm_name = "reserve-x16",
        .description = "Reserve X16",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x17)] = .{
        .llvm_name = "reserve-x17",
        .description = "Reserve X17",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x18)] = .{
        .llvm_name = "reserve-x18",
        .description = "Reserve X18",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x19)] = .{
        .llvm_name = "reserve-x19",
        .description = "Reserve X19",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x2)] = .{
        .llvm_name = "reserve-x2",
        .description = "Reserve X2",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x20)] = .{
        .llvm_name = "reserve-x20",
        .description = "Reserve X20",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x21)] = .{
        .llvm_name = "reserve-x21",
        .description = "Reserve X21",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x22)] = .{
        .llvm_name = "reserve-x22",
        .description = "Reserve X22",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x23)] = .{
        .llvm_name = "reserve-x23",
        .description = "Reserve X23",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x24)] = .{
        .llvm_name = "reserve-x24",
        .description = "Reserve X24",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x25)] = .{
        .llvm_name = "reserve-x25",
        .description = "Reserve X25",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x26)] = .{
        .llvm_name = "reserve-x26",
        .description = "Reserve X26",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x27)] = .{
        .llvm_name = "reserve-x27",
        .description = "Reserve X27",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x28)] = .{
        .llvm_name = "reserve-x28",
        .description = "Reserve X28",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x29)] = .{
        .llvm_name = "reserve-x29",
        .description = "Reserve X29",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x3)] = .{
        .llvm_name = "reserve-x3",
        .description = "Reserve X3",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x30)] = .{
        .llvm_name = "reserve-x30",
        .description = "Reserve X30",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x31)] = .{
        .llvm_name = "reserve-x31",
        .description = "Reserve X31",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x4)] = .{
        .llvm_name = "reserve-x4",
        .description = "Reserve X4",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x5)] = .{
        .llvm_name = "reserve-x5",
        .description = "Reserve X5",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x6)] = .{
        .llvm_name = "reserve-x6",
        .description = "Reserve X6",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x7)] = .{
        .llvm_name = "reserve-x7",
        .description = "Reserve X7",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x8)] = .{
        .llvm_name = "reserve-x8",
        .description = "Reserve X8",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.reserve_x9)] = .{
        .llvm_name = "reserve-x9",
        .description = "Reserve X9",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.rva20s64)] = .{
        .llvm_name = "rva20s64",
        .description = "RISC-V rva20s64 profile",
        .dependencies = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .ssccptr,
            .sstvala,
            .sstvecd,
            .svade,
            .svbare,
            .za128rs,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zifencei,
        }),
    };
    result[@backingInt(Feature.rva20u64)] = .{
        .llvm_name = "rva20u64",
        .description = "RISC-V rva20u64 profile",
        .dependencies = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .za128rs,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
        }),
    };
    result[@backingInt(Feature.rva22s64)] = .{
        .llvm_name = "rva22s64",
        .description = "RISC-V rva22s64 profile",
        .dependencies = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .b,
            .c,
            .d,
            .i,
            .m,
            .ssccptr,
            .sscounterenw,
            .sstvala,
            .sstvecd,
            .svade,
            .svbare,
            .svinval,
            .svpbmt,
            .za64rs,
            .zfhmin,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zifencei,
            .zihintpause,
            .zihpm,
            .zkt,
        }),
    };
    result[@backingInt(Feature.rva22u64)] = .{
        .llvm_name = "rva22u64",
        .description = "RISC-V rva22u64 profile",
        .dependencies = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .b,
            .c,
            .d,
            .i,
            .m,
            .za64rs,
            .zfhmin,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zihintpause,
            .zihpm,
            .zkt,
        }),
    };
    result[@backingInt(Feature.rva23s64)] = .{
        .llvm_name = "rva23s64",
        .description = "RISC-V rva23s64 profile",
        .dependencies = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .b,
            .c,
            .i,
            .m,
            .sha,
            .ssccptr,
            .sscofpmf,
            .sscounterenw,
            .ssnpm,
            .sstc,
            .sstvala,
            .sstvecd,
            .ssu64xl,
            .supm,
            .svade,
            .svbare,
            .svinval,
            .svnapot,
            .svpbmt,
            .v,
            .za64rs,
            .zawrs,
            .zcb,
            .zcmop,
            .zfa,
            .zfhmin,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zicond,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zimop,
            .zkt,
            .zvbb,
            .zvfhmin,
            .zvkt,
        }),
    };
    result[@backingInt(Feature.rva23u64)] = .{
        .llvm_name = "rva23u64",
        .description = "RISC-V rva23u64 profile",
        .dependencies = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .b,
            .c,
            .i,
            .m,
            .supm,
            .v,
            .za64rs,
            .zawrs,
            .zcb,
            .zcmop,
            .zfa,
            .zfhmin,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zicond,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zimop,
            .zkt,
            .zvbb,
            .zvfhmin,
            .zvkt,
        }),
    };
    result[@backingInt(Feature.rvb23s64)] = .{
        .llvm_name = "rvb23s64",
        .description = "RISC-V rvb23s64 profile",
        .dependencies = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .b,
            .c,
            .d,
            .i,
            .m,
            .ssccptr,
            .sscofpmf,
            .sscounterenw,
            .sstc,
            .sstvala,
            .sstvecd,
            .ssu64xl,
            .svade,
            .svbare,
            .svinval,
            .svnapot,
            .svpbmt,
            .za64rs,
            .zawrs,
            .zcb,
            .zcmop,
            .zfa,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zicond,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zimop,
            .zkt,
        }),
    };
    result[@backingInt(Feature.rvb23u64)] = .{
        .llvm_name = "rvb23u64",
        .description = "RISC-V rvb23u64 profile",
        .dependencies = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .b,
            .c,
            .d,
            .i,
            .m,
            .za64rs,
            .zawrs,
            .zcb,
            .zcmop,
            .zfa,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zicond,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zimop,
            .zkt,
        }),
    };
    result[@backingInt(Feature.rvi20u32)] = .{
        .llvm_name = "rvi20u32",
        .description = "RISC-V rvi20u32 profile",
        .dependencies = featureSet(&[_]Feature{
            .@"32bit",
            .i,
        }),
    };
    result[@backingInt(Feature.rvi20u64)] = .{
        .llvm_name = "rvi20u64",
        .description = "RISC-V rvi20u64 profile",
        .dependencies = featureSet(&[_]Feature{
            .@"64bit",
            .i,
        }),
    };
    result[@backingInt(Feature.save_restore)] = .{
        .llvm_name = "save-restore",
        .description = "Enable save/restore.",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.sdext)] = .{
        .llvm_name = "sdext",
        .description = "'Sdext' (External debugger)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.sdtrig)] = .{
        .llvm_name = "sdtrig",
        .description = "'Sdtrig' (Debugger triggers)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.sha)] = .{
        .llvm_name = "sha",
        .description = "'Sha' (Augmented Hypervisor)",
        .dependencies = featureSet(&[_]Feature{
            .h,
            .shcounterenw,
            .shgatpa,
            .shtvala,
            .shvsatpa,
            .shvstvala,
            .shvstvecd,
            .ssstateen,
        }),
    };
    result[@backingInt(Feature.shcounterenw)] = .{
        .llvm_name = "shcounterenw",
        .description = "'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.shgatpa)] = .{
        .llvm_name = "shgatpa",
        .description = "'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.shifted_zextw_fusion)] = .{
        .llvm_name = "shifted-zextw-fusion",
        .description = "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.shlcofideleg)] = .{
        .llvm_name = "shlcofideleg",
        .description = "'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.short_forward_branch_ialu)] = .{
        .llvm_name = "short-forward-branch-ialu",
        .description = "Enable short forward branch optimization for RVI base instructions",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.short_forward_branch_iload)] = .{
        .llvm_name = "short-forward-branch-iload",
        .description = "Enable short forward branch optimization for load instructions",
        .dependencies = featureSet(&[_]Feature{
            .short_forward_branch_ialu,
        }),
    };
    result[@backingInt(Feature.short_forward_branch_iminmax)] = .{
        .llvm_name = "short-forward-branch-iminmax",
        .description = "Enable short forward branch optimization for MIN,MAX instructions in Zbb",
        .dependencies = featureSet(&[_]Feature{
            .short_forward_branch_ialu,
        }),
    };
    result[@backingInt(Feature.short_forward_branch_imul)] = .{
        .llvm_name = "short-forward-branch-imul",
        .description = "Enable short forward branch optimization for MUL instruction",
        .dependencies = featureSet(&[_]Feature{
            .short_forward_branch_ialu,
        }),
    };
    result[@backingInt(Feature.shtvala)] = .{
        .llvm_name = "shtvala",
        .description = "'Shtvala' (htval provides all needed values)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.shvsatpa)] = .{
        .llvm_name = "shvsatpa",
        .description = "'Shvsatpa' (vsatp supports all modes supported by satp)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.shvstvala)] = .{
        .llvm_name = "shvstvala",
        .description = "'Shvstvala' (vstval provides all needed values)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.shvstvecd)] = .{
        .llvm_name = "shvstvecd",
        .description = "'Shvstvecd' (vstvec supports Direct mode)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.shxadd_load_fusion)] = .{
        .llvm_name = "shxadd-load-fusion",
        .description = "Enable SH(1|2|3)ADD(.UW) + load macrofusion",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.single_element_vec_fp64)] = .{
        .llvm_name = "single-element-vec-fp64",
        .description = "Certain vector FP64 operations produce a single result element per cycle",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.smaia)] = .{
        .llvm_name = "smaia",
        .description = "'Smaia' (Advanced Interrupt Architecture Machine Level)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.smcdeleg)] = .{
        .llvm_name = "smcdeleg",
        .description = "'Smcdeleg' (Counter Delegation Machine Level)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.smcntrpmf)] = .{
        .llvm_name = "smcntrpmf",
        .description = "'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.smcsrind)] = .{
        .llvm_name = "smcsrind",
        .description = "'Smcsrind' (Indirect CSR Access Machine Level)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.smctr)] = .{
        .llvm_name = "smctr",
        .description = "'Smctr' (Control Transfer Records Machine Level)",
        .dependencies = featureSet(&[_]Feature{
            .sscsrind,
        }),
    };
    result[@backingInt(Feature.smdbltrp)] = .{
        .llvm_name = "smdbltrp",
        .description = "'Smdbltrp' (Double Trap Machine Level)",
        .dependencies = featureSet(&[_]Feature{
            .zicsr,
        }),
    };
    result[@backingInt(Feature.smepmp)] = .{
        .llvm_name = "smepmp",
        .description = "'Smepmp' (Enhanced Physical Memory Protection)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.smmpm)] = .{
        .llvm_name = "smmpm",
        .description = "'Smmpm' (Machine-level Pointer Masking for M-mode)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.smnpm)] = .{
        .llvm_name = "smnpm",
        .description = "'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.smrnmi)] = .{
        .llvm_name = "smrnmi",
        .description = "'Smrnmi' (Resumable Non-Maskable Interrupts)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.smstateen)] = .{
        .llvm_name = "smstateen",
        .description = "'Smstateen' (Machine-mode view of the state-enable extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ssaia)] = .{
        .llvm_name = "ssaia",
        .description = "'Ssaia' (Advanced Interrupt Architecture Supervisor Level)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ssccfg)] = .{
        .llvm_name = "ssccfg",
        .description = "'Ssccfg' (Counter Configuration Supervisor Level)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ssccptr)] = .{
        .llvm_name = "ssccptr",
        .description = "'Ssccptr' (Main memory supports page table reads)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.sscofpmf)] = .{
        .llvm_name = "sscofpmf",
        .description = "'Sscofpmf' (Count Overflow and Mode-Based Filtering)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.sscounterenw)] = .{
        .llvm_name = "sscounterenw",
        .description = "'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.sscsrind)] = .{
        .llvm_name = "sscsrind",
        .description = "'Sscsrind' (Indirect CSR Access Supervisor Level)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ssctr)] = .{
        .llvm_name = "ssctr",
        .description = "'Ssctr' (Control Transfer Records Supervisor Level)",
        .dependencies = featureSet(&[_]Feature{
            .sscsrind,
        }),
    };
    result[@backingInt(Feature.ssdbltrp)] = .{
        .llvm_name = "ssdbltrp",
        .description = "'Ssdbltrp' (Double Trap Supervisor Level)",
        .dependencies = featureSet(&[_]Feature{
            .zicsr,
        }),
    };
    result[@backingInt(Feature.ssnpm)] = .{
        .llvm_name = "ssnpm",
        .description = "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.sspm)] = .{
        .llvm_name = "sspm",
        .description = "'Sspm' (Indicates Supervisor-mode Pointer Masking)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ssqosid)] = .{
        .llvm_name = "ssqosid",
        .description = "'Ssqosid' (Quality-of-Service (QoS) Identifiers)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ssstateen)] = .{
        .llvm_name = "ssstateen",
        .description = "'Ssstateen' (Supervisor-mode view of the state-enable extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ssstrict)] = .{
        .llvm_name = "ssstrict",
        .description = "'Ssstrict' (No non-conforming extensions are present)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.sstc)] = .{
        .llvm_name = "sstc",
        .description = "'Sstc' (Supervisor-mode timer interrupts)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.sstvala)] = .{
        .llvm_name = "sstvala",
        .description = "'Sstvala' (stval provides all needed values)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.sstvecd)] = .{
        .llvm_name = "sstvecd",
        .description = "'Sstvecd' (stvec supports Direct mode)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ssu64xl)] = .{
        .llvm_name = "ssu64xl",
        .description = "'Ssu64xl' (UXLEN=64 supported)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.supm)] = .{
        .llvm_name = "supm",
        .description = "'Supm' (Indicates User-mode Pointer Masking)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.svade)] = .{
        .llvm_name = "svade",
        .description = "'Svade' (Raise exceptions on improper A/D bits)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.svadu)] = .{
        .llvm_name = "svadu",
        .description = "'Svadu' (Hardware A/D updates)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.svbare)] = .{
        .llvm_name = "svbare",
        .description = "'Svbare' (satp mode Bare supported)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.svinval)] = .{
        .llvm_name = "svinval",
        .description = "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.svnapot)] = .{
        .llvm_name = "svnapot",
        .description = "'Svnapot' (NAPOT Translation Contiguity)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.svpbmt)] = .{
        .llvm_name = "svpbmt",
        .description = "'Svpbmt' (Page-Based Memory Types)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.svvptc)] = .{
        .llvm_name = "svvptc",
        .description = "'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.tagged_globals)] = .{
        .llvm_name = "tagged-globals",
        .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.unaligned_scalar_mem)] = .{
        .llvm_name = "unaligned-scalar-mem",
        .description = "Has reasonably performant unaligned scalar loads and stores",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.unaligned_vector_mem)] = .{
        .llvm_name = "unaligned-vector-mem",
        .description = "Has reasonably performant unaligned vector loads and stores",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.use_postra_scheduler)] = .{
        .llvm_name = "use-postra-scheduler",
        .description = "Schedule again after register allocation",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.v)] = .{
        .llvm_name = "v",
        .description = "'V' (Vector Extension for Application Processors)",
        .dependencies = featureSet(&[_]Feature{
            .zve64d,
            .zvl128b,
        }),
    };
    result[@backingInt(Feature.ventana_veyron)] = .{
        .llvm_name = "ventana-veyron",
        .description = "Ventana Veyron-Series processors",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.vl_dependent_latency)] = .{
        .llvm_name = "vl-dependent-latency",
        .description = "Latency of vector instructions is dependent on the dynamic value of vl",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.vxrm_pipeline_flush)] = .{
        .llvm_name = "vxrm-pipeline-flush",
        .description = "VXRM writes causes pipeline flush",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xandesbfhcvt)] = .{
        .llvm_name = "xandesbfhcvt",
        .description = "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)",
        .dependencies = featureSet(&[_]Feature{
            .f,
        }),
    };
    result[@backingInt(Feature.xandesperf)] = .{
        .llvm_name = "xandesperf",
        .description = "'XAndesPerf' (Andes Performance Extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xandesvbfhcvt)] = .{
        .llvm_name = "xandesvbfhcvt",
        .description = "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zve32f,
        }),
    };
    result[@backingInt(Feature.xandesvdot)] = .{
        .llvm_name = "xandesvdot",
        .description = "'XAndesVDot' (Andes Vector Dot Product Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.xandesvpackfph)] = .{
        .llvm_name = "xandesvpackfph",
        .description = "'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)",
        .dependencies = featureSet(&[_]Feature{
            .f,
        }),
    };
    result[@backingInt(Feature.xandesvsinth)] = .{
        .llvm_name = "xandesvsinth",
        .description = "'XAndesVSIntH' (Andes Vector Small INT Handling Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.xandesvsintload)] = .{
        .llvm_name = "xandesvsintload",
        .description = "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.xcvalu)] = .{
        .llvm_name = "xcvalu",
        .description = "'XCValu' (CORE-V ALU Operations)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xcvbi)] = .{
        .llvm_name = "xcvbi",
        .description = "'XCVbi' (CORE-V Immediate Branching)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xcvbitmanip)] = .{
        .llvm_name = "xcvbitmanip",
        .description = "'XCVbitmanip' (CORE-V Bit Manipulation)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xcvelw)] = .{
        .llvm_name = "xcvelw",
        .description = "'XCVelw' (CORE-V Event Load Word)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xcvmac)] = .{
        .llvm_name = "xcvmac",
        .description = "'XCVmac' (CORE-V Multiply-Accumulate)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xcvmem)] = .{
        .llvm_name = "xcvmem",
        .description = "'XCVmem' (CORE-V Post-incrementing Load & Store)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xcvsimd)] = .{
        .llvm_name = "xcvsimd",
        .description = "'XCVsimd' (CORE-V SIMD ALU)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xmipscbop)] = .{
        .llvm_name = "xmipscbop",
        .description = "'XMIPSCBOP' (MIPS Software Prefetch)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xmipscmov)] = .{
        .llvm_name = "xmipscmov",
        .description = "'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xmipsexectl)] = .{
        .llvm_name = "xmipsexectl",
        .description = "'XMIPSEXECTL' (MIPS execution control)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xmipslsp)] = .{
        .llvm_name = "xmipslsp",
        .description = "'XMIPSLSP' (MIPS optimization for hardware load-store bonding)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xqccmp)] = .{
        .llvm_name = "xqccmp",
        .description = "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xqci)] = .{
        .llvm_name = "xqci",
        .description = "'Xqci' (Qualcomm uC Extension)",
        .dependencies = featureSet(&[_]Feature{
            .xqcia,
            .xqciac,
            .xqcibi,
            .xqcibm,
            .xqcicli,
            .xqcicm,
            .xqcics,
            .xqcicsr,
            .xqciint,
            .xqciio,
            .xqcilb,
            .xqcili,
            .xqcilia,
            .xqcilo,
            .xqcilsm,
            .xqcisim,
            .xqcisls,
            .xqcisync,
        }),
    };
    result[@backingInt(Feature.xqcia)] = .{
        .llvm_name = "xqcia",
        .description = "'Xqcia' (Qualcomm uC Arithmetic Extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xqciac)] = .{
        .llvm_name = "xqciac",
        .description = "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xqcibi)] = .{
        .llvm_name = "xqcibi",
        .description = "'Xqcibi' (Qualcomm uC Branch Immediate Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xqcibm)] = .{
        .llvm_name = "xqcibm",
        .description = "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xqcicli)] = .{
        .llvm_name = "xqcicli",
        .description = "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xqcicm)] = .{
        .llvm_name = "xqcicm",
        .description = "'Xqcicm' (Qualcomm uC Conditional Move Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xqcics)] = .{
        .llvm_name = "xqcics",
        .description = "'Xqcics' (Qualcomm uC Conditional Select Extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xqcicsr)] = .{
        .llvm_name = "xqcicsr",
        .description = "'Xqcicsr' (Qualcomm uC CSR Extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xqciint)] = .{
        .llvm_name = "xqciint",
        .description = "'Xqciint' (Qualcomm uC Interrupts Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xqciio)] = .{
        .llvm_name = "xqciio",
        .description = "'Xqciio' (Qualcomm uC External Input Output Extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xqcilb)] = .{
        .llvm_name = "xqcilb",
        .description = "'Xqcilb' (Qualcomm uC Long Branch Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xqcili)] = .{
        .llvm_name = "xqcili",
        .description = "'Xqcili' (Qualcomm uC Load Large Immediate Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xqcilia)] = .{
        .llvm_name = "xqcilia",
        .description = "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xqcilo)] = .{
        .llvm_name = "xqcilo",
        .description = "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xqcilsm)] = .{
        .llvm_name = "xqcilsm",
        .description = "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xqcisim)] = .{
        .llvm_name = "xqcisim",
        .description = "'Xqcisim' (Qualcomm uC Simulation Hint Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xqcisls)] = .{
        .llvm_name = "xqcisls",
        .description = "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xqcisync)] = .{
        .llvm_name = "xqcisync",
        .description = "'Xqcisync' (Qualcomm uC Sync Delay Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.xsfcease)] = .{
        .llvm_name = "xsfcease",
        .description = "'XSfcease' (SiFive sf.cease Instruction)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xsfmm128t)] = .{
        .llvm_name = "xsfmm128t",
        .description = "'XSfmm128t' (TE=128 configuration)",
        .dependencies = featureSet(&[_]Feature{
            .xsfmmbase,
            .zvl512b,
        }),
    };
    result[@backingInt(Feature.xsfmm16t)] = .{
        .llvm_name = "xsfmm16t",
        .description = "'XSfmm16t' (TE=16 configuration)",
        .dependencies = featureSet(&[_]Feature{
            .xsfmmbase,
            .zvl64b,
        }),
    };
    result[@backingInt(Feature.xsfmm32a16f)] = .{
        .llvm_name = "xsfmm32a16f",
        .description = "'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF))",
        .dependencies = featureSet(&[_]Feature{
            .xsfmmbase,
            .zve32f,
        }),
    };
    result[@backingInt(Feature.xsfmm32a32f)] = .{
        .llvm_name = "xsfmm32a32f",
        .description = "'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b)",
        .dependencies = featureSet(&[_]Feature{
            .xsfmmbase,
            .zve32f,
        }),
    };
    result[@backingInt(Feature.xsfmm32a8f)] = .{
        .llvm_name = "xsfmm32a8f",
        .description = "'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8)",
        .dependencies = featureSet(&[_]Feature{
            .xsfmmbase,
            .zve32f,
        }),
    };
    result[@backingInt(Feature.xsfmm32a8i)] = .{
        .llvm_name = "xsfmm32a8i",
        .description = "'XSfmm32a8i' (TEW=32-bit accumulation, operands - int: 8b)",
        .dependencies = featureSet(&[_]Feature{
            .xsfmmbase,
        }),
    };
    result[@backingInt(Feature.xsfmm32t)] = .{
        .llvm_name = "xsfmm32t",
        .description = "'XSfmm32t' (TE=32 configuration)",
        .dependencies = featureSet(&[_]Feature{
            .xsfmmbase,
            .zvl128b,
        }),
    };
    result[@backingInt(Feature.xsfmm64a64f)] = .{
        .llvm_name = "xsfmm64a64f",
        .description = "'XSfmm64a64f' (TEW=64-bit accumulation, operands - float: fp64)",
        .dependencies = featureSet(&[_]Feature{
            .xsfmmbase,
            .zve64d,
        }),
    };
    result[@backingInt(Feature.xsfmm64t)] = .{
        .llvm_name = "xsfmm64t",
        .description = "'XSfmm64t' (TE=64 configuration)",
        .dependencies = featureSet(&[_]Feature{
            .xsfmmbase,
            .zvl256b,
        }),
    };
    result[@backingInt(Feature.xsfmmbase)] = .{
        .llvm_name = "xsfmmbase",
        .description = "'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.xsfvcp)] = .{
        .llvm_name = "xsfvcp",
        .description = "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.xsfvfbfexp16e)] = .{
        .llvm_name = "xsfvfbfexp16e",
        .description = "'XSfvfbfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, BFloat16)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xsfvfexp16e)] = .{
        .llvm_name = "xsfvfexp16e",
        .description = "'XSfvfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, Half Precision)",
        .dependencies = featureSet(&[_]Feature{
            .zvfh,
        }),
    };
    result[@backingInt(Feature.xsfvfexp32e)] = .{
        .llvm_name = "xsfvfexp32e",
        .description = "'XSfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction, Single Precision)",
        .dependencies = featureSet(&[_]Feature{
            .zve32f,
        }),
    };
    result[@backingInt(Feature.xsfvfexpa)] = .{
        .llvm_name = "xsfvfexpa",
        .description = "'XSfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)",
        .dependencies = featureSet(&[_]Feature{
            .zve32f,
        }),
    };
    result[@backingInt(Feature.xsfvfexpa64e)] = .{
        .llvm_name = "xsfvfexpa64e",
        .description = "'XSfvfexpa64e' (SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision)",
        .dependencies = featureSet(&[_]Feature{
            .xsfvfexpa,
            .zve64d,
        }),
    };
    result[@backingInt(Feature.xsfvfnrclipxfqf)] = .{
        .llvm_name = "xsfvfnrclipxfqf",
        .description = "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",
        .dependencies = featureSet(&[_]Feature{
            .zve32f,
        }),
    };
    result[@backingInt(Feature.xsfvfwmaccqqq)] = .{
        .llvm_name = "xsfvfwmaccqqq",
        .description = "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))",
        .dependencies = featureSet(&[_]Feature{
            .zvfbfmin,
            .zvl128b,
        }),
    };
    result[@backingInt(Feature.xsfvqmaccdod)] = .{
        .llvm_name = "xsfvqmaccdod",
        .description = "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
            .zvl128b,
        }),
    };
    result[@backingInt(Feature.xsfvqmaccqoq)] = .{
        .llvm_name = "xsfvqmaccqoq",
        .description = "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
            .zvl256b,
        }),
    };
    result[@backingInt(Feature.xsifivecdiscarddlone)] = .{
        .llvm_name = "xsifivecdiscarddlone",
        .description = "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xsifivecflushdlone)] = .{
        .llvm_name = "xsifivecflushdlone",
        .description = "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xsmtvdot)] = .{
        .llvm_name = "xsmtvdot",
        .description = "'XSMTVDot' (SpacemiT Vector Dot Product Extension)",
        .dependencies = featureSet(&[_]Feature{
            .zve32f,
        }),
    };
    result[@backingInt(Feature.xtheadba)] = .{
        .llvm_name = "xtheadba",
        .description = "'XTHeadBa' (T-Head address calculation instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xtheadbb)] = .{
        .llvm_name = "xtheadbb",
        .description = "'XTHeadBb' (T-Head basic bit-manipulation instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xtheadbs)] = .{
        .llvm_name = "xtheadbs",
        .description = "'XTHeadBs' (T-Head single-bit instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xtheadcmo)] = .{
        .llvm_name = "xtheadcmo",
        .description = "'XTHeadCmo' (T-Head cache management instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xtheadcondmov)] = .{
        .llvm_name = "xtheadcondmov",
        .description = "'XTHeadCondMov' (T-Head conditional move instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xtheadfmemidx)] = .{
        .llvm_name = "xtheadfmemidx",
        .description = "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xtheadmac)] = .{
        .llvm_name = "xtheadmac",
        .description = "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xtheadmemidx)] = .{
        .llvm_name = "xtheadmemidx",
        .description = "'XTHeadMemIdx' (T-Head Indexed Memory Operations)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xtheadmempair)] = .{
        .llvm_name = "xtheadmempair",
        .description = "'XTHeadMemPair' (T-Head two-GPR Memory Operations)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xtheadsync)] = .{
        .llvm_name = "xtheadsync",
        .description = "'XTHeadSync' (T-Head multicore synchronization instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xtheadvdot)] = .{
        .llvm_name = "xtheadvdot",
        .description = "'XTHeadVdot' (T-Head Vector Extensions for Dot)",
        .dependencies = featureSet(&[_]Feature{
            .v,
        }),
    };
    result[@backingInt(Feature.xventanacondops)] = .{
        .llvm_name = "xventanacondops",
        .description = "'XVentanaCondOps' (Ventana Conditional Ops)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.xwchc)] = .{
        .llvm_name = "xwchc",
        .description = "'Xwchc' (WCH/QingKe additional compressed opcodes)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.za128rs)] = .{
        .llvm_name = "za128rs",
        .description = "'Za128rs' (Reservation Set Size of at Most 128 Bytes)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.za64rs)] = .{
        .llvm_name = "za64rs",
        .description = "'Za64rs' (Reservation Set Size of at Most 64 Bytes)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zaamo)] = .{
        .llvm_name = "zaamo",
        .description = "'Zaamo' (Atomic Memory Operations)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zabha)] = .{
        .llvm_name = "zabha",
        .description = "'Zabha' (Byte and Halfword Atomic Memory Operations)",
        .dependencies = featureSet(&[_]Feature{
            .zaamo,
        }),
    };
    result[@backingInt(Feature.zacas)] = .{
        .llvm_name = "zacas",
        .description = "'Zacas' (Atomic Compare-And-Swap Instructions)",
        .dependencies = featureSet(&[_]Feature{
            .zaamo,
        }),
    };
    result[@backingInt(Feature.zalasr)] = .{
        .llvm_name = "zalasr",
        .description = "'Zalasr' (Load-Acquire and Store-Release Instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zalrsc)] = .{
        .llvm_name = "zalrsc",
        .description = "'Zalrsc' (Load-Reserved/Store-Conditional)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zama16b)] = .{
        .llvm_name = "zama16b",
        .description = "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zawrs)] = .{
        .llvm_name = "zawrs",
        .description = "'Zawrs' (Wait on Reservation Set)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zba)] = .{
        .llvm_name = "zba",
        .description = "'Zba' (Address Generation Instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zbb)] = .{
        .llvm_name = "zbb",
        .description = "'Zbb' (Basic Bit-Manipulation)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zbc)] = .{
        .llvm_name = "zbc",
        .description = "'Zbc' (Carry-Less Multiplication)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zbkb)] = .{
        .llvm_name = "zbkb",
        .description = "'Zbkb' (Bitmanip instructions for Cryptography)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zbkc)] = .{
        .llvm_name = "zbkc",
        .description = "'Zbkc' (Carry-less multiply instructions for Cryptography)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zbkx)] = .{
        .llvm_name = "zbkx",
        .description = "'Zbkx' (Crossbar permutation instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zbs)] = .{
        .llvm_name = "zbs",
        .description = "'Zbs' (Single-Bit Instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zca)] = .{
        .llvm_name = "zca",
        .description = "'Zca' (part of the C extension, excluding compressed floating point loads/stores)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zcb)] = .{
        .llvm_name = "zcb",
        .description = "'Zcb' (Compressed basic bit manipulation instructions)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.zcd)] = .{
        .llvm_name = "zcd",
        .description = "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
        .dependencies = featureSet(&[_]Feature{
            .d,
            .zca,
        }),
    };
    result[@backingInt(Feature.zce)] = .{
        .llvm_name = "zce",
        .description = "'Zce' (Compressed extensions for microcontrollers)",
        .dependencies = featureSet(&[_]Feature{
            .zcb,
            .zcmp,
            .zcmt,
        }),
    };
    result[@backingInt(Feature.zcf)] = .{
        .llvm_name = "zcf",
        .description = "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
        .dependencies = featureSet(&[_]Feature{
            .f,
            .zca,
        }),
    };
    result[@backingInt(Feature.zclsd)] = .{
        .llvm_name = "zclsd",
        .description = "'Zclsd' (Compressed Load/Store Pair Instructions)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
            .zilsd,
        }),
    };
    result[@backingInt(Feature.zcmop)] = .{
        .llvm_name = "zcmop",
        .description = "'Zcmop' (Compressed May-Be-Operations)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.zcmp)] = .{
        .llvm_name = "zcmp",
        .description = "'Zcmp' (sequenced instructions for code-size reduction)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
        }),
    };
    result[@backingInt(Feature.zcmt)] = .{
        .llvm_name = "zcmt",
        .description = "'Zcmt' (table jump instructions for code-size reduction)",
        .dependencies = featureSet(&[_]Feature{
            .zca,
            .zicsr,
        }),
    };
    result[@backingInt(Feature.zdinx)] = .{
        .llvm_name = "zdinx",
        .description = "'Zdinx' (Double in Integer)",
        .dependencies = featureSet(&[_]Feature{
            .zfinx,
        }),
    };
    result[@backingInt(Feature.zexth_fusion)] = .{
        .llvm_name = "zexth-fusion",
        .description = "Enable SLLI+SRLI to be fused to zero extension of halfword",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zextw_fusion)] = .{
        .llvm_name = "zextw-fusion",
        .description = "Enable SLLI+SRLI to be fused to zero extension of word",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zfa)] = .{
        .llvm_name = "zfa",
        .description = "'Zfa' (Additional Floating-Point)",
        .dependencies = featureSet(&[_]Feature{
            .f,
        }),
    };
    result[@backingInt(Feature.zfbfmin)] = .{
        .llvm_name = "zfbfmin",
        .description = "'Zfbfmin' (Scalar BF16 Converts)",
        .dependencies = featureSet(&[_]Feature{
            .f,
        }),
    };
    result[@backingInt(Feature.zfh)] = .{
        .llvm_name = "zfh",
        .description = "'Zfh' (Half-Precision Floating-Point)",
        .dependencies = featureSet(&[_]Feature{
            .zfhmin,
        }),
    };
    result[@backingInt(Feature.zfhmin)] = .{
        .llvm_name = "zfhmin",
        .description = "'Zfhmin' (Half-Precision Floating-Point Minimal)",
        .dependencies = featureSet(&[_]Feature{
            .f,
        }),
    };
    result[@backingInt(Feature.zfinx)] = .{
        .llvm_name = "zfinx",
        .description = "'Zfinx' (Float in Integer)",
        .dependencies = featureSet(&[_]Feature{
            .zicsr,
        }),
    };
    result[@backingInt(Feature.zhinx)] = .{
        .llvm_name = "zhinx",
        .description = "'Zhinx' (Half Float in Integer)",
        .dependencies = featureSet(&[_]Feature{
            .zhinxmin,
        }),
    };
    result[@backingInt(Feature.zhinxmin)] = .{
        .llvm_name = "zhinxmin",
        .description = "'Zhinxmin' (Half Float in Integer Minimal)",
        .dependencies = featureSet(&[_]Feature{
            .zfinx,
        }),
    };
    result[@backingInt(Feature.zic64b)] = .{
        .llvm_name = "zic64b",
        .description = "'Zic64b' (Cache Block Size Is 64 Bytes)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zicbom)] = .{
        .llvm_name = "zicbom",
        .description = "'Zicbom' (Cache-Block Management Instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zicbop)] = .{
        .llvm_name = "zicbop",
        .description = "'Zicbop' (Cache-Block Prefetch Instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zicboz)] = .{
        .llvm_name = "zicboz",
        .description = "'Zicboz' (Cache-Block Zero Instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ziccamoa)] = .{
        .llvm_name = "ziccamoa",
        .description = "'Ziccamoa' (Main Memory Supports All Atomics in A)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ziccamoc)] = .{
        .llvm_name = "ziccamoc",
        .description = "'Ziccamoc' (Main Memory Supports Atomics in Zacas)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ziccif)] = .{
        .llvm_name = "ziccif",
        .description = "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zicclsm)] = .{
        .llvm_name = "zicclsm",
        .description = "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ziccrse)] = .{
        .llvm_name = "ziccrse",
        .description = "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zicntr)] = .{
        .llvm_name = "zicntr",
        .description = "'Zicntr' (Base Counters and Timers)",
        .dependencies = featureSet(&[_]Feature{
            .zicsr,
        }),
    };
    result[@backingInt(Feature.zicond)] = .{
        .llvm_name = "zicond",
        .description = "'Zicond' (Integer Conditional Operations)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zicsr)] = .{
        .llvm_name = "zicsr",
        .description = "'Zicsr' (CSRs)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zifencei)] = .{
        .llvm_name = "zifencei",
        .description = "'Zifencei' (fence.i)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zihintntl)] = .{
        .llvm_name = "zihintntl",
        .description = "'Zihintntl' (Non-Temporal Locality Hints)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zihintpause)] = .{
        .llvm_name = "zihintpause",
        .description = "'Zihintpause' (Pause Hint)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zihpm)] = .{
        .llvm_name = "zihpm",
        .description = "'Zihpm' (Hardware Performance Counters)",
        .dependencies = featureSet(&[_]Feature{
            .zicsr,
        }),
    };
    result[@backingInt(Feature.zilsd)] = .{
        .llvm_name = "zilsd",
        .description = "'Zilsd' (Load/Store Pair Instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zilsd_4byte_align)] = .{
        .llvm_name = "zilsd-4byte-align",
        .description = "Allow 4-byte alignment for Zilsd LD/SD instructions",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zimop)] = .{
        .llvm_name = "zimop",
        .description = "'Zimop' (May-Be-Operations)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zk)] = .{
        .llvm_name = "zk",
        .description = "'Zk' (Standard scalar cryptography extension)",
        .dependencies = featureSet(&[_]Feature{
            .zkn,
            .zkr,
            .zkt,
        }),
    };
    result[@backingInt(Feature.zkn)] = .{
        .llvm_name = "zkn",
        .description = "'Zkn' (NIST Algorithm Suite)",
        .dependencies = featureSet(&[_]Feature{
            .zbkb,
            .zbkc,
            .zbkx,
            .zknd,
            .zkne,
            .zknh,
        }),
    };
    result[@backingInt(Feature.zknd)] = .{
        .llvm_name = "zknd",
        .description = "'Zknd' (NIST Suite: AES Decryption)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zkne)] = .{
        .llvm_name = "zkne",
        .description = "'Zkne' (NIST Suite: AES Encryption)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zknh)] = .{
        .llvm_name = "zknh",
        .description = "'Zknh' (NIST Suite: Hash Function Instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zkr)] = .{
        .llvm_name = "zkr",
        .description = "'Zkr' (Entropy Source Extension)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zks)] = .{
        .llvm_name = "zks",
        .description = "'Zks' (ShangMi Algorithm Suite)",
        .dependencies = featureSet(&[_]Feature{
            .zbkb,
            .zbkc,
            .zbkx,
            .zksed,
            .zksh,
        }),
    };
    result[@backingInt(Feature.zksed)] = .{
        .llvm_name = "zksed",
        .description = "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zksh)] = .{
        .llvm_name = "zksh",
        .description = "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zkt)] = .{
        .llvm_name = "zkt",
        .description = "'Zkt' (Data Independent Execution Latency)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zmmul)] = .{
        .llvm_name = "zmmul",
        .description = "'Zmmul' (Integer Multiplication)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.ztso)] = .{
        .llvm_name = "ztso",
        .description = "'Ztso' (Memory Model - Total Store Order)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zvbb)] = .{
        .llvm_name = "zvbb",
        .description = "'Zvbb' (Vector basic bit-manipulation instructions)",
        .dependencies = featureSet(&[_]Feature{
            .zvkb,
        }),
    };
    result[@backingInt(Feature.zvbc)] = .{
        .llvm_name = "zvbc",
        .description = "'Zvbc' (Vector Carryless Multiplication)",
        .dependencies = featureSet(&[_]Feature{
            .zve64x,
        }),
    };
    result[@backingInt(Feature.zve32f)] = .{
        .llvm_name = "zve32f",
        .description = "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)",
        .dependencies = featureSet(&[_]Feature{
            .f,
            .zve32x,
        }),
    };
    result[@backingInt(Feature.zve32x)] = .{
        .llvm_name = "zve32x",
        .description = "'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)",
        .dependencies = featureSet(&[_]Feature{
            .zicsr,
            .zvl32b,
        }),
    };
    result[@backingInt(Feature.zve64d)] = .{
        .llvm_name = "zve64d",
        .description = "'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)",
        .dependencies = featureSet(&[_]Feature{
            .d,
            .zve64f,
        }),
    };
    result[@backingInt(Feature.zve64f)] = .{
        .llvm_name = "zve64f",
        .description = "'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)",
        .dependencies = featureSet(&[_]Feature{
            .zve32f,
            .zve64x,
        }),
    };
    result[@backingInt(Feature.zve64x)] = .{
        .llvm_name = "zve64x",
        .description = "'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
            .zvl64b,
        }),
    };
    result[@backingInt(Feature.zvfbfmin)] = .{
        .llvm_name = "zvfbfmin",
        .description = "'Zvfbfmin' (Vector BF16 Converts)",
        .dependencies = featureSet(&[_]Feature{
            .zve32f,
        }),
    };
    result[@backingInt(Feature.zvfbfwma)] = .{
        .llvm_name = "zvfbfwma",
        .description = "'Zvfbfwma' (Vector BF16 widening mul-add)",
        .dependencies = featureSet(&[_]Feature{
            .zfbfmin,
            .zvfbfmin,
        }),
    };
    result[@backingInt(Feature.zvfh)] = .{
        .llvm_name = "zvfh",
        .description = "'Zvfh' (Vector Half-Precision Floating-Point)",
        .dependencies = featureSet(&[_]Feature{
            .zfhmin,
            .zvfhmin,
        }),
    };
    result[@backingInt(Feature.zvfhmin)] = .{
        .llvm_name = "zvfhmin",
        .description = "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
        .dependencies = featureSet(&[_]Feature{
            .zve32f,
        }),
    };
    result[@backingInt(Feature.zvkb)] = .{
        .llvm_name = "zvkb",
        .description = "'Zvkb' (Vector Bit-manipulation used in Cryptography)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.zvkg)] = .{
        .llvm_name = "zvkg",
        .description = "'Zvkg' (Vector GCM instructions for Cryptography)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.zvkn)] = .{
        .llvm_name = "zvkn",
        .description = "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')",
        .dependencies = featureSet(&[_]Feature{
            .zvkb,
            .zvkned,
            .zvknhb,
            .zvkt,
        }),
    };
    result[@backingInt(Feature.zvknc)] = .{
        .llvm_name = "zvknc",
        .description = "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
        .dependencies = featureSet(&[_]Feature{
            .zvbc,
            .zvkn,
        }),
    };
    result[@backingInt(Feature.zvkned)] = .{
        .llvm_name = "zvkned",
        .description = "'Zvkned' (Vector AES Encryption & Decryption (Single Round))",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.zvkng)] = .{
        .llvm_name = "zvkng",
        .description = "'Zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
        .dependencies = featureSet(&[_]Feature{
            .zvkg,
            .zvkn,
        }),
    };
    result[@backingInt(Feature.zvknha)] = .{
        .llvm_name = "zvknha",
        .description = "'Zvknha' (Vector SHA-2 (SHA-256 only))",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.zvknhb)] = .{
        .llvm_name = "zvknhb",
        .description = "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
        .dependencies = featureSet(&[_]Feature{
            .zve64x,
        }),
    };
    result[@backingInt(Feature.zvks)] = .{
        .llvm_name = "zvks",
        .description = "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')",
        .dependencies = featureSet(&[_]Feature{
            .zvkb,
            .zvksed,
            .zvksh,
            .zvkt,
        }),
    };
    result[@backingInt(Feature.zvksc)] = .{
        .llvm_name = "zvksc",
        .description = "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
        .dependencies = featureSet(&[_]Feature{
            .zvbc,
            .zvks,
        }),
    };
    result[@backingInt(Feature.zvksed)] = .{
        .llvm_name = "zvksed",
        .description = "'Zvksed' (SM4 Block Cipher Instructions)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.zvksg)] = .{
        .llvm_name = "zvksg",
        .description = "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
        .dependencies = featureSet(&[_]Feature{
            .zvkg,
            .zvks,
        }),
    };
    result[@backingInt(Feature.zvksh)] = .{
        .llvm_name = "zvksh",
        .description = "'Zvksh' (SM3 Hash Function Instructions)",
        .dependencies = featureSet(&[_]Feature{
            .zve32x,
        }),
    };
    result[@backingInt(Feature.zvkt)] = .{
        .llvm_name = "zvkt",
        .description = "'Zvkt' (Vector Data-Independent Execution Latency)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zvl1024b)] = .{
        .llvm_name = "zvl1024b",
        .description = "'Zvl1024b' (Minimum Vector Length 1024)",
        .dependencies = featureSet(&[_]Feature{
            .zvl512b,
        }),
    };
    result[@backingInt(Feature.zvl128b)] = .{
        .llvm_name = "zvl128b",
        .description = "'Zvl128b' (Minimum Vector Length 128)",
        .dependencies = featureSet(&[_]Feature{
            .zvl64b,
        }),
    };
    result[@backingInt(Feature.zvl16384b)] = .{
        .llvm_name = "zvl16384b",
        .description = "'Zvl16384b' (Minimum Vector Length 16384)",
        .dependencies = featureSet(&[_]Feature{
            .zvl8192b,
        }),
    };
    result[@backingInt(Feature.zvl2048b)] = .{
        .llvm_name = "zvl2048b",
        .description = "'Zvl2048b' (Minimum Vector Length 2048)",
        .dependencies = featureSet(&[_]Feature{
            .zvl1024b,
        }),
    };
    result[@backingInt(Feature.zvl256b)] = .{
        .llvm_name = "zvl256b",
        .description = "'Zvl256b' (Minimum Vector Length 256)",
        .dependencies = featureSet(&[_]Feature{
            .zvl128b,
        }),
    };
    result[@backingInt(Feature.zvl32768b)] = .{
        .llvm_name = "zvl32768b",
        .description = "'Zvl32768b' (Minimum Vector Length 32768)",
        .dependencies = featureSet(&[_]Feature{
            .zvl16384b,
        }),
    };
    result[@backingInt(Feature.zvl32b)] = .{
        .llvm_name = "zvl32b",
        .description = "'Zvl32b' (Minimum Vector Length 32)",
        .dependencies = featureSet(&[_]Feature{}),
    };
    result[@backingInt(Feature.zvl4096b)] = .{
        .llvm_name = "zvl4096b",
        .description = "'Zvl4096b' (Minimum Vector Length 4096)",
        .dependencies = featureSet(&[_]Feature{
            .zvl2048b,
        }),
    };
    result[@backingInt(Feature.zvl512b)] = .{
        .llvm_name = "zvl512b",
        .description = "'Zvl512b' (Minimum Vector Length 512)",
        .dependencies = featureSet(&[_]Feature{
            .zvl256b,
        }),
    };
    result[@backingInt(Feature.zvl64b)] = .{
        .llvm_name = "zvl64b",
        .description = "'Zvl64b' (Minimum Vector Length 64)",
        .dependencies = featureSet(&[_]Feature{
            .zvl32b,
        }),
    };
    result[@backingInt(Feature.zvl65536b)] = .{
        .llvm_name = "zvl65536b",
        .description = "'Zvl65536b' (Minimum Vector Length 65536)",
        .dependencies = featureSet(&[_]Feature{
            .zvl32768b,
        }),
    };
    result[@backingInt(Feature.zvl8192b)] = .{
        .llvm_name = "zvl8192b",
        .description = "'Zvl8192b' (Minimum Vector Length 8192)",
        .dependencies = featureSet(&[_]Feature{
            .zvl4096b,
        }),
    };
    const ti = @typeInfo(Feature);
    for (&result, 0..) |*elem, i| {
        elem.index = i;
        elem.name = ti.@"enum".field_names[i];
    }
    break :blk result;
};

pub const cpu = struct {
    pub const andes_45_series: CpuModel = .{
        .name = "andes_45_series",
        .llvm_name = "andes-45-series",
        .features = featureSet(&[_]Feature{
            .andes45,
            .no_default_unroll,
            .short_forward_branch_ialu,
            .use_postra_scheduler,
        }),
    };
    pub const andes_a25: CpuModel = .{
        .name = "andes_a25",
        .llvm_name = "andes-a25",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .xandesperf,
            .zifencei,
        }),
    };
    pub const andes_a45: CpuModel = .{
        .name = "andes_a45",
        .llvm_name = "andes-a45",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .andes45,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .short_forward_branch_ialu,
            .use_postra_scheduler,
            .xandesperf,
            .zifencei,
        }),
    };
    pub const andes_ax25: CpuModel = .{
        .name = "andes_ax25",
        .llvm_name = "andes-ax25",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .xandesperf,
            .zifencei,
        }),
    };
    pub const andes_ax45: CpuModel = .{
        .name = "andes_ax45",
        .llvm_name = "andes-ax45",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .andes45,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .short_forward_branch_ialu,
            .use_postra_scheduler,
            .xandesperf,
            .zifencei,
        }),
    };
    pub const andes_ax45mpv: CpuModel = .{
        .name = "andes_ax45mpv",
        .llvm_name = "andes-ax45mpv",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .andes45,
            .c,
            .i,
            .m,
            .no_default_unroll,
            .short_forward_branch_ialu,
            .use_postra_scheduler,
            .v,
            .xandesperf,
            .zifencei,
        }),
    };
    pub const andes_n45: CpuModel = .{
        .name = "andes_n45",
        .llvm_name = "andes-n45",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .andes45,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .short_forward_branch_ialu,
            .use_postra_scheduler,
            .xandesperf,
            .zifencei,
        }),
    };
    pub const andes_nx45: CpuModel = .{
        .name = "andes_nx45",
        .llvm_name = "andes-nx45",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .andes45,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .short_forward_branch_ialu,
            .use_postra_scheduler,
            .xandesperf,
            .zifencei,
        }),
    };
    pub const baseline_rv32: CpuModel = .{
        .name = "baseline_rv32",
        .llvm_name = null,
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .d,
            .i,
            .m,
        }),
    };
    pub const baseline_rv64: CpuModel = .{
        .name = "baseline_rv64",
        .llvm_name = null,
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
        }),
    };
    pub const generic: CpuModel = .{
        .name = "generic",
        .llvm_name = "generic",
        .features = featureSet(&[_]Feature{}),
    };
    pub const generic_ooo: CpuModel = .{
        .name = "generic_ooo",
        .llvm_name = "generic-ooo",
        .features = featureSet(&[_]Feature{}),
    };
    pub const generic_rv32: CpuModel = .{
        .name = "generic_rv32",
        .llvm_name = "generic-rv32",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .i,
            .optimized_nf2_segment_load_store,
        }),
    };
    pub const generic_rv64: CpuModel = .{
        .name = "generic_rv64",
        .llvm_name = "generic-rv64",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .i,
            .optimized_nf2_segment_load_store,
        }),
    };
    pub const mips_p8700: CpuModel = .{
        .name = "mips_p8700",
        .llvm_name = "mips-p8700",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .mips_p8700,
            .xmipscbop,
            .xmipscmov,
            .xmipsexectl,
            .xmipslsp,
            .zba,
            .zbb,
            .zifencei,
        }),
    };
    pub const rocket: CpuModel = .{
        .name = "rocket",
        .llvm_name = "rocket",
        .features = featureSet(&[_]Feature{}),
    };
    pub const rocket_rv32: CpuModel = .{
        .name = "rocket_rv32",
        .llvm_name = "rocket-rv32",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .i,
            .zicsr,
            .zifencei,
        }),
    };
    pub const rocket_rv64: CpuModel = .{
        .name = "rocket_rv64",
        .llvm_name = "rocket-rv64",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .i,
            .zicsr,
            .zifencei,
        }),
    };
    pub const rp2350_hazard3: CpuModel = .{
        .name = "rp2350_hazard3",
        .llvm_name = "rp2350-hazard3",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .i,
            .m,
            .zba,
            .zbb,
            .zbkb,
            .zbs,
            .zcb,
            .zcmp,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_7_series: CpuModel = .{
        .name = "sifive_7_series",
        .llvm_name = "sifive-7-series",
        .features = featureSet(&[_]Feature{
            .no_default_unroll,
            .short_forward_branch_ialu,
            .use_postra_scheduler,
        }),
    };
    pub const sifive_e20: CpuModel = .{
        .name = "sifive_e20",
        .llvm_name = "sifive-e20",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .c,
            .i,
            .m,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_e21: CpuModel = .{
        .name = "sifive_e21",
        .llvm_name = "sifive-e21",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .i,
            .m,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_e24: CpuModel = .{
        .name = "sifive_e24",
        .llvm_name = "sifive-e24",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .f,
            .i,
            .m,
            .zifencei,
        }),
    };
    pub const sifive_e31: CpuModel = .{
        .name = "sifive_e31",
        .llvm_name = "sifive-e31",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .i,
            .m,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_e34: CpuModel = .{
        .name = "sifive_e34",
        .llvm_name = "sifive-e34",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .f,
            .i,
            .m,
            .zifencei,
        }),
    };
    pub const sifive_e76: CpuModel = .{
        .name = "sifive_e76",
        .llvm_name = "sifive-e76",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .f,
            .i,
            .m,
            .no_default_unroll,
            .short_forward_branch_ialu,
            .use_postra_scheduler,
            .zifencei,
        }),
    };
    pub const sifive_p450: CpuModel = .{
        .name = "sifive_p450",
        .llvm_name = "sifive-p450",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .auipc_addi_fusion,
            .b,
            .c,
            .conditional_cmv_fusion,
            .d,
            .i,
            .lui_addi_fusion,
            .m,
            .no_default_unroll,
            .unaligned_scalar_mem,
            .unaligned_vector_mem,
            .use_postra_scheduler,
            .za64rs,
            .zfhmin,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zkt,
        }),
    };
    pub const sifive_p470: CpuModel = .{
        .name = "sifive_p470",
        .llvm_name = "sifive-p470",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .auipc_addi_fusion,
            .b,
            .c,
            .conditional_cmv_fusion,
            .i,
            .lui_addi_fusion,
            .m,
            .no_default_unroll,
            .no_sink_splat_operands,
            .unaligned_scalar_mem,
            .unaligned_vector_mem,
            .use_postra_scheduler,
            .v,
            .vxrm_pipeline_flush,
            .xsifivecdiscarddlone,
            .xsifivecflushdlone,
            .za64rs,
            .zfhmin,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zkt,
            .zvbb,
            .zvknc,
            .zvkng,
            .zvksc,
            .zvksg,
        }),
    };
    pub const sifive_p550: CpuModel = .{
        .name = "sifive_p550",
        .llvm_name = "sifive-p550",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .auipc_addi_fusion,
            .c,
            .conditional_cmv_fusion,
            .d,
            .i,
            .lui_addi_fusion,
            .m,
            .no_default_unroll,
            .use_postra_scheduler,
            .zba,
            .zbb,
            .zifencei,
        }),
    };
    pub const sifive_p670: CpuModel = .{
        .name = "sifive_p670",
        .llvm_name = "sifive-p670",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .auipc_addi_fusion,
            .b,
            .c,
            .conditional_cmv_fusion,
            .i,
            .lui_addi_fusion,
            .m,
            .no_default_unroll,
            .no_sink_splat_operands,
            .unaligned_scalar_mem,
            .unaligned_vector_mem,
            .use_postra_scheduler,
            .v,
            .vxrm_pipeline_flush,
            .za64rs,
            .zfhmin,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zkt,
            .zvbb,
            .zvknc,
            .zvkng,
            .zvksc,
            .zvksg,
        }),
    };
    pub const sifive_p870: CpuModel = .{
        .name = "sifive_p870",
        .llvm_name = "sifive-p870",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .auipc_addi_fusion,
            .b,
            .c,
            .conditional_cmv_fusion,
            .i,
            .lui_addi_fusion,
            .m,
            .no_default_unroll,
            .no_sink_splat_operands,
            .supm,
            .unaligned_scalar_mem,
            .unaligned_vector_mem,
            .use_postra_scheduler,
            .v,
            .vxrm_pipeline_flush,
            .za64rs,
            .zama16b,
            .zawrs,
            .zcb,
            .zcmop,
            .zfa,
            .zfh,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zicond,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zimop,
            .zkr,
            .zkt,
            .zvbb,
            .zvfbfwma,
            .zvfh,
            .zvknc,
            .zvkng,
            .zvksc,
            .zvksg,
        }),
    };
    pub const sifive_s21: CpuModel = .{
        .name = "sifive_s21",
        .llvm_name = "sifive-s21",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .i,
            .m,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_s51: CpuModel = .{
        .name = "sifive_s51",
        .llvm_name = "sifive-s51",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .i,
            .m,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_s54: CpuModel = .{
        .name = "sifive_s54",
        .llvm_name = "sifive-s54",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .zifencei,
        }),
    };
    pub const sifive_s76: CpuModel = .{
        .name = "sifive_s76",
        .llvm_name = "sifive-s76",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .short_forward_branch_ialu,
            .use_postra_scheduler,
            .zifencei,
            .zihintpause,
        }),
    };
    pub const sifive_u54: CpuModel = .{
        .name = "sifive_u54",
        .llvm_name = "sifive-u54",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .zifencei,
        }),
    };
    pub const sifive_u74: CpuModel = .{
        .name = "sifive_u74",
        .llvm_name = "sifive-u74",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .short_forward_branch_ialu,
            .use_postra_scheduler,
            .zifencei,
        }),
    };
    pub const sifive_x280: CpuModel = .{
        .name = "sifive_x280",
        .llvm_name = "sifive-x280",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .dlen_factor_2,
            .i,
            .m,
            .no_default_unroll,
            .optimized_nf2_segment_load_store,
            .optimized_zero_stride_load,
            .short_forward_branch_ialu,
            .use_postra_scheduler,
            .v,
            .vl_dependent_latency,
            .zba,
            .zbb,
            .zfh,
            .zifencei,
            .zvfh,
            .zvl512b,
        }),
    };
    pub const sifive_x390: CpuModel = .{
        .name = "sifive_x390",
        .llvm_name = "sifive-x390",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .b,
            .c,
            .dlen_factor_2,
            .experimental_zicfilp,
            .experimental_zicfiss,
            .i,
            .m,
            .no_default_unroll,
            .optimized_nf2_segment_load_store,
            .optimized_zero_stride_load,
            .short_forward_branch_ialu,
            .single_element_vec_fp64,
            .use_postra_scheduler,
            .v,
            .vl_dependent_latency,
            .xsifivecdiscarddlone,
            .xsifivecflushdlone,
            .za64rs,
            .zawrs,
            .zcb,
            .zcmop,
            .zfa,
            .zfh,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .ziccrse,
            .zicntr,
            .zicond,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zkr,
            .zkt,
            .zvbb,
            .zvfbfwma,
            .zvfh,
            .zvkt,
            .zvl1024b,
        }),
    };
    pub const spacemit_a100: CpuModel = .{
        .name = "spacemit_a100",
        .llvm_name = null,
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .b,
            .c,
            .dlen_factor_2,
            .i,
            .m,
            .optimized_nf2_segment_load_store,
            .optimized_nf3_segment_load_store,
            .optimized_nf4_segment_load_store,
            .smepmp,
            .smnpm,
            .smstateen,
            .ssccptr,
            .sscofpmf,
            .sscounterenw,
            .ssnpm,
            .sspm,
            .sstc,
            .sstvala,
            .sstvecd,
            .ssu64xl,
            .supm,
            .svade,
            .svbare,
            .svinval,
            .svnapot,
            .svpbmt,
            .unaligned_scalar_mem,
            .v,
            .vxrm_pipeline_flush,
            .za64rs,
            .zawrs,
            .zbc,
            .zbkc,
            .zcb,
            .zcmop,
            .zfa,
            .zfh,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zicond,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zimop,
            .zkt,
            .zvbb,
            .zvfbfwma,
            .zvfh,
            .zvkng,
            .zvknha,
            .zvksc,
            .zvksg,
            .zvl1024b,
        }),
    };
    pub const spacemit_x100: CpuModel = .{
        .name = "spacemit_x100",
        .llvm_name = null,
        .features = featureSet(&[_]Feature{
            .dlen_factor_2,
            .optimized_nf2_segment_load_store,
            .optimized_nf3_segment_load_store,
            .optimized_nf4_segment_load_store,
            .rva23s64,
            .smepmp,
            .smnpm,
            .smstateen,
            .sspm,
            .unaligned_scalar_mem,
            .vxrm_pipeline_flush,
            .xsmtvdot,
            .zbc,
            .zbkc,
            .zfh,
            .zvfbfwma,
            .zvfh,
            .zvkng,
            .zvknha,
            .zvksc,
            .zvksg,
            .zvl256b,
        }),
    };
    pub const spacemit_x60: CpuModel = .{
        .name = "spacemit_x60",
        .llvm_name = "spacemit-x60",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .b,
            .c,
            .dlen_factor_2,
            .i,
            .m,
            .optimized_nf2_segment_load_store,
            .optimized_nf3_segment_load_store,
            .optimized_nf4_segment_load_store,
            .ssccptr,
            .sscofpmf,
            .sscounterenw,
            .sstc,
            .sstvala,
            .sstvecd,
            .svade,
            .svbare,
            .svinval,
            .svnapot,
            .svpbmt,
            .unaligned_scalar_mem,
            .v,
            .vxrm_pipeline_flush,
            .xsmtvdot,
            .za64rs,
            .zbc,
            .zbkc,
            .zfh,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zicond,
            .zifencei,
            .zihintpause,
            .zihpm,
            .zkt,
            .zvfh,
            .zvkt,
            .zvl256b,
        }),
    };
    pub const syntacore_scr1_base: CpuModel = .{
        .name = "syntacore_scr1_base",
        .llvm_name = "syntacore-scr1-base",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .c,
            .i,
            .no_default_unroll,
            .zicsr,
            .zifencei,
        }),
    };
    pub const syntacore_scr1_max: CpuModel = .{
        .name = "syntacore_scr1_max",
        .llvm_name = "syntacore-scr1-max",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .c,
            .i,
            .m,
            .no_default_unroll,
            .zicsr,
            .zifencei,
        }),
    };
    pub const syntacore_scr3_rv32: CpuModel = .{
        .name = "syntacore_scr3_rv32",
        .llvm_name = "syntacore-scr3-rv32",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .c,
            .i,
            .m,
            .no_default_unroll,
            .use_postra_scheduler,
            .zicsr,
            .zifencei,
        }),
    };
    pub const syntacore_scr3_rv64: CpuModel = .{
        .name = "syntacore_scr3_rv64",
        .llvm_name = "syntacore-scr3-rv64",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .i,
            .m,
            .no_default_unroll,
            .use_postra_scheduler,
            .zicsr,
            .zifencei,
        }),
    };
    pub const syntacore_scr4_rv32: CpuModel = .{
        .name = "syntacore_scr4_rv32",
        .llvm_name = "syntacore-scr4-rv32",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .use_postra_scheduler,
            .zifencei,
        }),
    };
    pub const syntacore_scr4_rv64: CpuModel = .{
        .name = "syntacore_scr4_rv64",
        .llvm_name = "syntacore-scr4-rv64",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .use_postra_scheduler,
            .zifencei,
        }),
    };
    pub const syntacore_scr5_rv32: CpuModel = .{
        .name = "syntacore_scr5_rv32",
        .llvm_name = "syntacore-scr5-rv32",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .use_postra_scheduler,
            .zifencei,
        }),
    };
    pub const syntacore_scr5_rv64: CpuModel = .{
        .name = "syntacore_scr5_rv64",
        .llvm_name = "syntacore-scr5-rv64",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .use_postra_scheduler,
            .zifencei,
        }),
    };
    pub const syntacore_scr7: CpuModel = .{
        .name = "syntacore_scr7",
        .llvm_name = "syntacore-scr7",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .i,
            .m,
            .no_default_unroll,
            .use_postra_scheduler,
            .v,
            .zba,
            .zbb,
            .zbc,
            .zbs,
            .zifencei,
            .zkn,
        }),
    };
    pub const tt_ascalon_d8: CpuModel = .{
        .name = "tt_ascalon_d8",
        .llvm_name = "tt-ascalon-d8",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .b,
            .c,
            .i,
            .log_vrgather,
            .m,
            .no_default_unroll,
            .optimized_nf2_segment_load_store,
            .optimized_nf3_segment_load_store,
            .optimized_nf4_segment_load_store,
            .optimized_nf5_segment_load_store,
            .optimized_nf6_segment_load_store,
            .optimized_nf7_segment_load_store,
            .optimized_nf8_segment_load_store,
            .optimized_zero_stride_load,
            .sha,
            .smaia,
            .ssaia,
            .ssccptr,
            .sscofpmf,
            .sscounterenw,
            .ssnpm,
            .ssstrict,
            .sstc,
            .sstvala,
            .sstvecd,
            .ssu64xl,
            .supm,
            .svade,
            .svbare,
            .svinval,
            .svnapot,
            .svpbmt,
            .unaligned_scalar_mem,
            .unaligned_vector_mem,
            .use_postra_scheduler,
            .v,
            .za64rs,
            .zawrs,
            .zcb,
            .zcmop,
            .zfa,
            .zfh,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zicond,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zimop,
            .zkt,
            .zvbb,
            .zvbc,
            .zvfbfwma,
            .zvfh,
            .zvkng,
            .zvl256b,
        }),
    };
    pub const veyron_v1: CpuModel = .{
        .name = "veyron_v1",
        .llvm_name = "veyron-v1",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .add_load_fusion,
            .auipc_addi_fusion,
            .auipc_load_fusion,
            .c,
            .d,
            .disable_misched_load_clustering,
            .disable_postmisched_load_clustering,
            .disable_postmisched_store_clustering,
            .i,
            .lui_addi_fusion,
            .lui_load_fusion,
            .m,
            .shifted_zextw_fusion,
            .ventana_veyron,
            .xventanacondops,
            .zba,
            .zbb,
            .zbc,
            .zbs,
            .zexth_fusion,
            .zextw_fusion,
            .zicbom,
            .zicbop,
            .zicboz,
            .zicntr,
            .zifencei,
            .zihintpause,
            .zihpm,
        }),
    };
    pub const xiangshan_kunminghu: CpuModel = .{
        .name = "xiangshan_kunminghu",
        .llvm_name = "xiangshan-kunminghu",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .b,
            .c,
            .i,
            .m,
            .no_default_unroll,
            .sha,
            .shifted_zextw_fusion,
            .smaia,
            .smcsrind,
            .smdbltrp,
            .smmpm,
            .smnpm,
            .smrnmi,
            .smstateen,
            .ssaia,
            .ssccptr,
            .sscofpmf,
            .sscounterenw,
            .sscsrind,
            .ssdbltrp,
            .ssnpm,
            .sspm,
            .ssstrict,
            .sstc,
            .sstvala,
            .sstvecd,
            .ssu64xl,
            .supm,
            .svade,
            .svbare,
            .svinval,
            .svnapot,
            .svpbmt,
            .v,
            .za64rs,
            .zacas,
            .zawrs,
            .zbc,
            .zcb,
            .zcmop,
            .zexth_fusion,
            .zextw_fusion,
            .zfa,
            .zfh,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zicond,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zimop,
            .zkn,
            .zks,
            .zkt,
            .zvbb,
            .zvfh,
            .zvkt,
        }),
    };
    pub const xiangshan_nanhu: CpuModel = .{
        .name = "xiangshan_nanhu",
        .llvm_name = "xiangshan-nanhu",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .shifted_zextw_fusion,
            .svinval,
            .zba,
            .zbb,
            .zbc,
            .zbs,
            .zexth_fusion,
            .zextw_fusion,
            .zicbom,
            .zicboz,
            .zifencei,
            .zkn,
            .zksed,
            .zksh,
        }),
    };
};
